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Scalable low-power 1-bit hybrid full adder for fast computation using Pass Transistors

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Prof. Dr. Reena Singh, Aher Vijaya Navnath, Dr. Bibhab Kumar Lodh
» doi: 10.31838/ecb/2023.12.si6.067


Using pass transistor logic, we constructed a 1-bit full adder circuit in this study. High-speed technology uses pass transistor logic, and it is simple to construct the fundamental gate architectures. An improvement on the pass transistor logic Ex-or gate is the designed circuit. The I-V characteristics and power for sum and carry were computed for the 1-bit Full Adder Circuit. The performance assessment of a 1-bit full adder circuit allows for the analysis of the impact of scaling on overall performance. In order to compare the functionality of the proposed full adder circuit with the conventional design and to ensure its efficacy, simulations have been performed on the LT Spice tool simulator at 1.8v single ended supply voltage. The results show that the circuit has low power dissipation at high speeds.

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