A new design of Phase-Locked Loop (PLL) with multiple outputs in low power and high speed has designed with Noise Efficient System. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. The input 1Mhz - frequency of this PLL gotten external source is able to generate multiple frequencies provided for the circuits of communication standard in high-speed Integrated Circuits, such as Serial Peripheral Interface (SPI - 128MHz), Two-wire Interface (I2C-Ultra fast mode 5Mhz), etc. The PLL is designed with a 45nm CMOS technology and verified under parasitic extraction. The results of this design are shown less than 1mW power consumption and the out range of 4Mhz to 128Mhz during 25-50oC temperature