Compressors are the fundamental components in the partial product reduction stage of CMOS multipliers. A new design is presented for the CMOS 5-2 compressor with 58 transistors, which is the lowest reported device count for such a circuit. Simulation results show that the proposed 5-2 compressor has significantly improved power-delay performance compared to previously proposed approaches. The overall design is performed in DSCH and Microwind 65nm technology and individual block is examined before designing the 5-2 compressor.