Nowadays the emergence for high speed digital system in VLSI industry and the integration of more number of processing blocks – regulating the data flow and switching activity is becoming most challenging task than ever and significantly affect both circuit life and reliability. The System-on-Chip (SoC) application comes with the integration several Intellectual Property (IP) cores to meet the desired functionality. To reduce the number of interconnection and associated power consumption in system on chip (SoC) application network on-chip plays vital role to regulate the traffic among different IP components. In this paer Dynamic Partial Reconfiguration (DPR) is propsoed in NOC router design to maximize the data rate and regulate the traffic rate inside the digital system. Finally to reduce the switching activity the memory components associated to router design the FIFO memory blocks are replaced with valid and request based hand shake protocol is used inside the Network-on-Chip (NoC). It also includes FSM based high level parameterization to select the most suitable NoC configuration size to reduce the computational complexity overhead and leads improved system reconfigurability to maximize the system performance. In addition to this Reconfigurability during NOC routing highly flexible NoCs and enables full customization for dynamic reconfigurable applications. An increasingly popular option for multi-IP systems-on-chip is networking over chip (NoC)-based communication. Many improvements have been made to the NoC's adoption of FPGA-based, dynamically reconfigurable IPs. One method to lower the power usage of the NoC's idle components is to use a run-time scalable NoC that uses dynamic partial reconfiguration (DPR). Nevertheless, the issue of specialised HDL NoC creation tools that divide the NoC rows and columns into distinct components is still unresolved. In this research, we present an approach to describe and build runtime scalable NoC components for Xilinx FPGAs based on UML, MARTÉ, and IPXACT. In order to model the NoC, it is divided into static sub-NoCs and a component consisting of a sequence of run-time scalable rows and columns.